1. Field of the Invention
Embodiments of the invention relate to nonvolatile semiconductor memories. More particularly, embodiments of the invention relate to a multilevel nonvolatile semiconductor memory capable of storing data of two or more bits in one memory cell.
2. Description of the Related Art
A recently rapid development of information processing apparatuses such as a computer, etc. tends to bring about a high-speed operation and large capacity in semiconductor memory devices employed as main components of the information processing apparatuses.
Typically a semiconductor memory device may be largely classified as a volatile semiconductor memory device and a nonvolatile semiconductor memory device. The volatile semiconductor memory device may be subdivided into a dynamic random access memory and a static random access memory. The volatile semiconductor memory device is fast in read and write speed, but has a shortcoming that contents stored in memory cells are lost when an external power supply is cut off. Conversely, nonvolatile semiconductor memory devices may be classified as mask read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
Such nonvolatile semiconductor memory devices have been typically used to store data even without external power. However, in the MROM, PROM, and EPROM, erase and write (or program) operations can not be executed through the electronic system itself. Thus making it difficult to erase or re-program programmed-contents in an on-board state. In an EEPROM, electrical erase and write operations are available through the system itself. This allows EEPROMs to be used as system program storage devices or auxiliary storage devices. Various types of electronic devices controlled by a computer or micro-processor require the development of high density electrically erasable and programmable EEPROMs. A data storage device used in, for example, a digital camera, must be compact, have a relatively higher density and higher performance characteristics.
A NAND-type flash EEPROM having a flash erase function appearing as the design and fabrication technique of EEPROM has been advanced which has a high integration as compared to a general EEPROM and is very advantageous to an application to a large-capacity auxiliary memory. The flash EEPROM is classified as NAND, NOR and AND types, depending upon what kinds of types in unit memory cell arrays are configured. It is well known that NAND type memory has high integration as compared to NOR or AND type.
A configuration of a general nonvolatile semiconductor memory device and fabrication sections of memory cells in a memory cell array are disclosed in, for example, U.S. Pat. No. 6,295,227 (“the '227 patent”) published on Sep. 25, 2001. As disclosed in the '227 patent, a NAND type EEPROM may be comprised of a data input/output buffer, a row decoder for selecting word lines, a column decoder, a column gate, a page buffer for sensing and storing input/output data of memory cell transistors, a booster circuit for generating a boosted voltage, a control circuit for controlling operation of a memory device, and a memory cell array. The memory cell array includes word lines that intersect bit lines. Each memory cell transistor of a NAND cell unit (or cell string) stores data. The word lines control gates of the selected transistors and the memory cell transistors of the NAND cell unit.
A NAND cell unit is formed in a p-type well formed on an n type well. The NAND cell unit constituting a unit of one string is defined by a first selection transistor SST whose drain is connected to a bit line, a second selection transistor ST whose source is connected to a common source line, and 16 or 32 memory transistors whose channels are connected in series between a source of the first selection transistor SST and a drain of the second selection transistor ST. Each memory cell transistor constituting a NAND cell unit has a floating gate formed by interposing a gate oxide on a channel region between a source and a drain, and a control gate formed on the floating gate FG through an interlayer insulation layer. Charge functioning as program data through a program voltage applied to the control gate CG is gathered in floating gate FG.
The erase and program (or write) operations are performed by using F-N tunneling current. For example, in order to erase a memory cell, a very high potential is applied to a substrate and a low potential is applied to control gate CG. The potential determined by a coupling ratio of a capacitance between CG and FG and a capacitance between FG and the substrate is applied to the floating gate FG. When a potential difference between a floating gate voltage Vfg and a substrate voltage Vsub is greater than a potential difference creating the F-N tunneling, electrons gathered in the floating gate FG move to the substrate. This lowers a threshold voltage Vt of a memory cell transistor. Voltage Vt is sufficiently lowered and 0 V is applied to the control gate CG and the source. When an appropriate level of voltage is applied to the drain, current flows. This is commonly referred to as “ERASED” and is generally represented as logic ‘1’.
In order to write to a memory cell, 0V is applied to the source and drain and a very high voltage is applied to the control gate CG. An inversion layer is formed in channel region and the source and drain both have a potential of 0V. When a potential difference between Vchannel (0 V) and Vfg, which is determined on the basis of the coupling ratio of the capacitance between the control gate CG and the floating gate FG and the capacitance between the floating gate FG and the channel region (of the substrate), becomes enough to create F-N tunneling, electrons move from the channel region to the floating gate FG. In this manner, voltage Vt increases and when a predetermined level of voltage is applied to the CG, 0V is applied to the source, and an appropriate level of voltage is applied to the drain. This prevents current flow and is referred to as “PROGRAMMED” indicated as logic ‘0’.
In the memory cell array, a page indicates memory cell transistors in which control gates are connected in common to a particular word line. Multiple pages include a plurality of memory cell transistors defining a cell block. A cell block unit generally includes one or a plurality of cell strings per bit line. The NAND flash memory has a page program mode to accommodate high speed programming. A page program operation is classified as a data loading operation and program operation. The data loading operation sequentially latches and stores, in data registers, data of a byte magnitude from input/output terminals. The data registers are referred to as a page buffer and correspond to the number of bit lines. The program operation includes simultaneously writing the data stored in the data registers to memory transistors associated with a selected word line through selected bit lines.
In the NAND-type EEPROM described above, read operation and program (write) operation are generally performed by a page unit. The erase operation is performed by a block unit. In particular, electron movement between a channel and a FG of the memory cell transistor appears only in the program and erase operations. In the read operation, data stored in a memory cell transistor is just read without damaging the data after the program and erase operations have been performed. In the read operation, a predetermined voltage (typically, a ground voltage) is applied to CG of a selected memory cell transistor and a voltage (typically, a read voltage) higher than the predetermined voltage is applied to CG of a non-selected memory cell transistor. Current flows or does not flow in a corresponding bit line according to a program state of the selected memory cell transistor. When a threshold voltage of the programmed memory cell is higher than a reference value under a predetermined voltage condition, the memory cell is an off-cell, thereby charging a corresponding bit line to a high voltage level. Conversely, when a threshold voltage of the programmed memory cell is lower than a reference value, the memory cell is an on-cell, and a corresponding bit line is discharged to a low level. A state of such a bit line is read out as ‘0’ or ‘1’ through a sense amplifier.
Increases in memory capacity have resulted in multilevel cell (MLC) technology in which data of 2 bits (i.e. four states) or more are programmed or stored in a single memory cell of, for example, a NAND type EEPROM. A threshold voltage of a floating gate MOS transistor defining one memory cell may have one of the four states by appropriately controlling the number of electrons injected into a floating gate in a multilevel program operating mode. In a multilevel read mode, a voltage which indicates a medium from among threshold voltages of four states, is applied as a primary read reference voltage. This is used to sense whether a selected memory cell belongs to a high state or a low state. Subsequently, two different secondary-read reference voltages are used to sense whether the memory cell has a most significant state among the high states or a least significant state among the low states.
Details for such multilevel NAND cell type flash memory are disclosed in U.S. Pat. No. 6,807,096 issued on Oct. 19, 2004 and U.S. Pat. No. 6,937,510 issued on Aug. 30, 2005 which is provided herein for reference only. A multilevel NAND flash memory has a page program mode for high-speed programs. FIG. 1 provides a multi-page programming method in a multilevel flash memory according to a conventional art. FIG. 2 illustrates timings related to the multi-page program illustrated in FIG. 1. FIG. 3 illustrates a distribution change of threshold voltage generally appearing in a multilevel data program.
Referring to FIG. 1 a method of ‘multi-page program’ is disclosed to simultaneously program four pages of data in order to increase programming speed in a multilevel NAND flash memory having four banks 1, 2, 3 and 4. Page data for the four banks are loaded into corresponding page buffers 60-63 in respective steps S1, S2, S3 and S4. The four banks are simultaneously selected and a program operation is performed into designated pages of respective banks through step S5. This page programming method is primarily used to shorten a program time per page in a multilevel flash memory based on a considerably low programming speed.
FIG. 2 illustrates timing diagrams provided when programming four pages through such multi-page program step sections S1, S2, S3, S4 and S5 related to the loading and programming associated with steps S1, S2, S3, S4 and S5 of FIG. 1. Step S1 includes in order, a time interval C1 receiving a data load command, time interval C2 receiving an address, time interval C3 receiving program data and time interval C4 receiving a program command. Program data is loaded into page buffers 60-63 corresponding to a respective bank in steps S1, S2, S3 and S4. In step S5, blocks 10-13 are selected at the same time to perform programming operations.
FIG. 3 illustrates a distribution change of threshold voltage generally appearing in a multilevel data program. A transverse axis indicates a threshold voltage of a memory cell, and a longitudinal axis indicates the number of programmed memory cells. In a flash memory that stores 2 bits of data in one memory cell, data of respective cells are allocated into mutually different pages. A graph (a) of FIG. 3 denotes a program operation of least significant bit (LSB) data. A voltage stepping of ISPP (Incremental Step Program Pulse) is determined largely in order to speed up the program. Then, a comparatively wide threshold voltage distribution is obtained. This type of programming method is called an “SLC Program”. An LSB-programmed cell has a wider threshold voltage distribution in a step that adjacent cells are programmed, as shown in a graph (b) of FIG. 3, as compared with the graph (a). Graph (c) of FIG. 3 denotes programming operation of most significant bit (MSB) data. Of the cells left in the erase state after the programming of LSB data ‘1’, a cell into which an MSB data ‘0’ is loaded moves to a state of ‘01’ as shown in an arrow AR1. Of the cells into which LSB data ‘0’ is programmed, a cell into which MSB data ‘1’ is loaded moves to a state of ‘10’ as shown in an arrow AR2. Of the cells into which LSB data ‘0’ is programmed, a cell into which MSB data ‘0’ is loaded moves to a state of ‘00’ as shown in an arrow AR3. Accordingly, in the programming step of adjacent cells after the LSB program, the threshold voltage distribution effect becomes wide to compensate for a disturbance and a threshold voltage distribution can be controlled more precisely. In such a programming method, the LSB page program can be obtained earlier by making the ISPP program voltage step greater, but the MSB page program has a considerably lower programming speed as compared with the LSB page program because it needs to precisely control three threshold voltage states. For example, when an LSB page program time tLSB is 200 μs, and an MSB page program time tMSB is 1400 μs where an average page program time becomes tPGM=(tLSB+tMSB)/2=800 μs. As a result, in the multi-page programming method as illustrated in FIG. 1, four pages are programmed at a time such that the average program time is 800 μs/4=200 μs. In the programming method of FIG. 1, a program unit becomes four pages. Consequently, a controller can provide efficient program performance when data for four pages are loaded and programmed at a time. When the program unit becomes large, an overall program time can be shortened with this enhanced program performance. However, the large program unit may have an inefficient aspect in view of managing a file system. It is, therefore, required to find a method to increase a program speed while maintaining a smaller program unit. Accordingly, there is a need for a method to enhance program speed while keeping a relatively smaller program unit in a multilevel flash memory.